An FPGA-Based Implementation of HW/SW architecture for CFAR Radar Target Detector

Conference Paper

2011

Published in: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6177358

, Ridha Djemal . 2011

This paper presents an efficient HW/SW Codesign
FPGA-based architecture of B-ACOSD CFAR target detector in
log normal distribution for radar system. All CFAR system
modules are analyzed in order to identify the critical ones to be
optimized so that the detection process will be conducted in realtime.
To compel the design optimization of CFAR Architecture,
we have considered the custom instruction approach offered by
Altera environment. Furthermore HW/SW architecture of the
CFAR detector is carried out where the NIOS II execute the
software part and communicate via the Avalon switch fabric with
the hardware modules represented by the custom logic
components, on-chip memories, UART and JTAG interfaces.
The proposed system-on-chip is validated and tested using the
Stratix IV EP4SGX230KF4C2 of Altera operating at 250MHz.
Using the HW/SW approach for our embedded target detection
system, we improved the performance of the architecture
compared to the pure software one with a total delay of 0.45 µs

• Publication Work Type: ماجستير