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Ayed Saad Alqahtani

Assistant Professor

Computer Engineering Department

علوم الحاسب والمعلومات
Building 31, Office No. 2229

AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs

Alqahtani, Ayed . 2018

The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve area, performance, power, and scalability of many-core systems. However, reliability issue as a perpetual challenge in advanced silicon technology imperils it. Aging is an emerging reliability concern, which degrades the system's performance and causes timing failure eventually. Bias-Temperature-Instability (BTI) and Hot-Carrier-Injection (HCI) are the dominant aging mechanisms, which escalate in high temperature and stress (i.e., usage). In addition to the intra-layer temperature variations, 3D NoCs experience inter-layer temperature variations, which demand necessary investigations for aging as compared to 2D NoC. In this paper, we propose AROMa, an aging-aware deadlock-free adaptive routing algorithm integrated with a novel online aging monitoring system for 3D NoCs. The monitoring system in AROMa exploits Distributed-Centralized-Aging-Table (D-CAT) to obtain routers' aging rates for each layer of 3D NoCs periodically. Consequently, AROMa swaps between different k-best source-destination shortest paths periodically to avoid highly aged routers, force them in recovery phase of BTI, and accordingly balance aging in the network. We prove that AROMa is deadlock free. Our extensive experimental analysis using gem5 full system mode for PARSEC and SPLASH-2 benchmark suites concludes that AROMa outperforms state-of-the-art works while improving age imbalance by 70 percent and maximum age by 35 percent in 3D NoC with negligible overheads.

Volume Number
29
Issue Number
4
Magazine \ Newspaper
IEEE Transactions on Parallel and Distributed Systems
Pages
772-788
more of publication
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While 3-D integrated circuits (ICs) offer many advantages over 2-D ICs, thermal management challenges remain unresolved. Thermal through-silicon-vias (TTSVs) are TSVs that facilitate heat transfer…

by Ayed Alqahtani, Zongqing Ren, N. Bagherzadeh, J. Lee
2020
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3D stacking of integrated circuits (ICs) provides significant advantages in saving device footprints, improving power management, and continuing performance enhancement, particularly for many-core…

by Ayed Alqahtani, Zongqing Ren, N. Bagherzadeh, J. Lee
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The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve area, performance, power, and scalability of many-core systems. However, reliability issue as a perpetual…

by Ayed Alqahtani, Z. Ghaderi, N. Bagherzadeh
2018