1. “Experimental Investigation of Low‐Jitter and Wide‐Band Dual Cascaded PLL System” (American Institute of Physics-API) IAENG TRANSACTIONS ON ENGINEERING TECHNOLOGIES VOLUME 6 ‐ SPECIAL EDITION OF THE WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE 20
(American Institute of Physics-API
Matrix multiplication is the kernel operation used in many image
and signal processing applications. In this paper, we present the
design and Field Programmable Gate Array (FPGA)
implementation of matrix multiplier architectures for use in
image and signal processing applications. The designs are
optimized for speed which is the main requirement in these
applications. First design involves computation of dense matrixvector multiplication which is used in image processing
application. The design has been implemented on Virtex-4 FPGA
and the performance is evaluated by computing the execution
time on FPGA. Implementation results demonstrate that it can
provide a throughput of 16970 frames per second which is quite
adequate for most image processing applications. The second
design involves multiplication of tri-matrix (three matrices)
which is used in signal processing application. The proposed
design for the multiplication of three matrices has been
implemented on Spartan-3 and Virtex-II Pro platform FPGAs
respectively. Implementation results are presented which
demonstrate the suitability of FPGAs for such applications.
Key words:
FPGA, Matrix Multiplier, Systolic Array, VLSI.
Matrix multiplication is the kernel operation used in many image
and signal processing applications. In this paper, we present the
design and Field Programmable Gate Array (FPGA)…