Course Objectives:

The main objectives of this course are to introduce students to the Binary system representation and conversion of numbers in order to perform arithmetic and logic operations, and to perform gate level minimization for the combinational logic. In addition the students have to study the synchronous sequential logic including flip flop and latches in order to consider registers and counters with some applications.

Topics Covered:

Binary system representation including conversion between different systems and arithmetic and logic operations; Boolean algebra and logic gates representations, Gate Level minimization using the K-map with and without don’t care conditions; Combinational Logic including adders, multipliers; Synchronous sequential logic; Registers and counters.

**Textbook: Digital Design by M. Morris Mano, Prentice Hall, Latest edition**

Course outline:

1- Number Systems

2-Boolean Algebra &Logic gates

3-Boolean functions and simplification

4- Combinational logic circuits

5- MSI & PLD Components

6-Sequential circuits

7-Registers, counters& memory units

*Course Schedule*

Week |
Topics to be covered |

1 | Introduction to Logic Design, Course Outline. Lecture: Number Systems.Lecture: |

2 | Number SystemsLecture: Computer ArithmeticLecture: Signed Arithmetic, Two’s and One’s Compliment, OverflowLecture: |

3 | Switching Algebra and Switching Logic GatesLecture: Switching NetworkLecture: Representation of Logic FunctionsLecture: |

4 | Representation of Logic Functions Lecture:Assignment 1 Sum-of-Product and Product-of-Sum, Minterms and MaxtermsLecture: Combinational Logic MinimizationLecture: |

5 | Karnaugh MapLecture: Assignment 2 K-Map and Prime ImplicantLecture: Don’t Cares and K-MapLecture: |

6 | Building Blocks of Combinational LogicLecture: Assignment 3 Adders and SubtractorsLecture: Decoders and Encoders,Lecture: |

7 | Lecture:Midterm Exam I, Assignment 4 Priority EncodingLecture: MultiplexersLecture: |

8-9 | Holiday – Eid Al-Adha Break |

10 | Sequential Blocks, Latches and Flipflops,Lecture: Sequential State MachinesLecture: Mealy and Moore State MachinesLecture: |

11 | Finite State Machine AnalysisLecture: Finite State Machine Design with DFFLecture: Finite State Machine Design with JKFFLecture: |

12 | Lecture:Midterm Exam II, Assignment 5 Finite State Machine Design ExamplesLecture: Finite State Machine Design ExamplesLecture: |

13 | More Sequential Circuits,Lecture: Registers, Universal Shift Registers,Lecture: Counters, Sequential PLDsLecture: |

14 | Memory DesignLecture: Memory DesignLecture:Lecture: Review |

16 | Final Exam – Comprehensive |

**Student Evaluation Plan**

Tutorial and Homework | 10% |

Quizzes | 10% |

Midterm Exam(s) | 40% |

Final Exam | 40% |

Total |
100% |