EE 208

Course Objectives:
The main objectives of this course are to introduce students to the Binary system representation and conversion of numbers in order to perform arithmetic and logic operations, and to perform gate level minimization for the combinational logic. In addition the students have to study the synchronous sequential logic including flip flop and latches in order to consider registers and counters with some applications.

Topics Covered:
Binary system representation including conversion between different systems and arithmetic and logic operations; Boolean algebra and logic gates representations, Gate Level minimization using the K-map with and without don’t care conditions; Combinational Logic including adders, multipliers; Synchronous sequential logic; Registers and counters.

Textbook: Digital Design by M. Morris Mano, Prentice Hall, Latest edition

Course outline:

1- Number Systems

2-Boolean Algebra &Logic gates

3-Boolean functions and simplification

4- Combinational logic circuits

5- MSI & PLD Components

6-Sequential circuits

7-Registers, counters& memory units

Course Schedule

 Week Topics to be covered 1 Lecture: Introduction to Logic Design, Course Outline. Lecture: Number Systems. 2 Lecture: Number SystemsLecture: Computer ArithmeticLecture: Signed Arithmetic, Two’s and One’s Compliment, Overflow 3 Lecture: Switching Algebra and Switching Logic GatesLecture: Switching NetworkLecture: Representation of Logic Functions 4 Lecture: Representation of Logic Functions Assignment 1Lecture: Sum-of-Product and Product-of-Sum, Minterms and MaxtermsLecture: Combinational Logic Minimization 5 Lecture: Karnaugh Map Assignment 2Lecture: K-Map and Prime ImplicantLecture: Don’t Cares and K-Map 6 Lecture: Building Blocks of Combinational Logic Assignment 3Lecture: Adders and SubtractorsLecture: Decoders and Encoders, 7 Lecture: Midterm Exam I, Assignment 4Lecture: Priority EncodingLecture: Multiplexers 8-9 Holiday – Eid Al-Adha Break 10 Lecture: Sequential Blocks, Latches and Flipflops,Lecture: Sequential State MachinesLecture: Mealy and Moore State Machines 11 Lecture: Finite State Machine AnalysisLecture: Finite State Machine Design with DFFLecture: Finite State Machine Design with JKFF 12 Lecture: Midterm Exam II, Assignment 5Lecture: Finite State Machine Design ExamplesLecture: Finite State Machine Design Examples 13 Lecture: More Sequential Circuits,Lecture: Registers, Universal Shift Registers,Lecture: Counters, Sequential PLDs 14 Lecture: Memory DesignLecture: Memory DesignLecture: Review 16 Final Exam – Comprehensive

Student Evaluation Plan

 Tutorial and Homework 10% Quizzes 10% Midterm Exam(s) 40% Final Exam 40% Total 100%
Course Materials