Logic Design
Textbook: M. Morris Mano, Digital Design, Prentice Hall Edition, 2005.
Description: Signals and Signal Processing, Discrete-Time Signals and Systems in the Time-Domain and Frequency-Domain, Digital Processing of Continuous-Time Signals, Digital Filter Structures, Digital Filter Design, and Applications.
Course Objectives: The main objectives of this course are to introduce students to the Binary system representation and conversion of numbers in order to perform arithmetic and logic operations, and to perform gate level minimization for the combinational logic. In addition the students have to study the synchronous sequential logic including flip flop and latches in order to consider registers and counters with some applications.
Topics: Binary system representation including conversion between different systems and arithmetic and logic operations; Boolean algebra and logic gates representations, Gate Level minimization using the K-map with and without don’t care conditions; Combinational Logic including adders, multipliers; Synchronous sequential logic; Registers and counters.
Class/Tutorial Schedule: Class is held three times per week in 50-minute lecture sessions. There is also a 50-minute weekly tutorial associated with this course.
Relation to Program Objectives: This course contributes to the general objectives listed for an Electrical Engineering Department.
This course contains six chapters as following;
Chapter 1: Binary Systems
1.1 Introduction to Digital Systems
1.2 Binary Numbers
1.3 Number Base Conversions (Integers and Fractions)
1.4 Octal and Hexadecimal Numbers
1.5 Arithmetic operations in bases (ADD, SUB and Mult)
1.6 1’s and 2’s Complement
1.7 Binary codes (BCD, Gray, ASCII)
1.8 Logic gates
Chapter 2: Boolean Algebra and Logic Gates
2.1 Basic Definitions
2.2 Boolean Algebra
2.3 Boolean Algebra Theorems
2.4 Boolean functions and truth tables
2.5 Canonical and Standard forms
2.6 Logic operations
2.7 Digital Logic gates
Chapter 3: Gate Level Minimization
3.1 The Map method
3.2 Four-variable Map
3.3 Five-variable Map
3.4 Product of Sums Simplification
3.5 Don’t-Care conditions
3.6 NAND and NOR Implementation
3.7 Other Two-level Implementation
3.8 XOR function
Chapter 4: Combinational Logic
4.1 Combinational Circuits
4.2 Analysis Procedure
4.3 Design Procedures
4.4 Binary Adder-Substractor
4.5 Binary Multiplier
4.6 Magnitude Comparator
4.7 Decoders
4.8 Encoders
4.9 Mutiplexers
Chapter 5: Synchronous Sequential logic
5.1 Sequential Circuits
5.2 Latches
5.3 Flip Flops
5.4 Analysis of clocked sequential circuits
5.5 Design Procedure
Chapter 6: Registers and Counters
6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Others counters
6.7 Applications of counters
Evaluation
20% Quizzes and Tutorial
40% Two Mid-Term Exam
40% Final Exam
Preparer: Associate Professor Ridha Ahmed DJEMAL
Last Revision: September 2007.