تجاوز إلى المحتوى الرئيسي
User Image

Hussein Khalid Al-Hussein

Associate Professor

Associate Professor

علوم الحاسب والمعلومات
Building 31, 2nd floor, Office 2209
مادة دراسية

CEN313: Logic Design and HDL

This course provides students with required knowledge of modeling of digital systems in Verilog. It covers both combinational and sequential systems at the gate levels such as logic gates and flip-flops and the building blocks level such as full adders, decoders, shift registers, and finite state machines.

ملحقات المادة الدراسية