Appendix F
VHDL code for testing Microcontroller with
USB interface
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------
entity PICOBLAZE_WITH_USB is
PORT (
RST : in std_logic;
USB_D : inout std_logic_vector(7 downto 0);
USB_RXF : in std_logic;
USB_TXE : in std_logic;
USB_RD : out std_logic;
USB_WR : out std_logic;
SWS : in std_logic_vector(7 downto 0);
LEDS : out std_logic_vector(7 downto 0);
CLK : in std_logic
);
end PICOBLAZE_WITH_USB;
architecture Behavioral of PICOBLAZE_WITH_USB is
----------------------------------------------------------------------------------
-- declaration of KCPSM3
----------------------------------------------------------------------------------
component kcpsm3 is
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
----------------------------------------------------------------------------------
-- declaration of program ROM
----------------------------------------------------------------------------------
component rom_0 is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end component;
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic :='0';
signal interrupt_ack : std_logic;
--
----------------------------------------------------------------------------------
-- Signals used to connect KCPSM3 to USB/FIFO interface
----------------------------------------------------------------------------------
signal usb_data: std_logic_vector(7 downto 0):= (others=> 'Z');
signal usb_ctrl: std_logic_vector(7 downto 0):= (others=> '0');
signal usb_rd_ena : std_logic;
signal sws_int: std_logic_vector(7 downto 0);
signal leds_int: std_logic_vector(7 downto 0):= (others=>'0');
--
--
signal reset_kcpsm3: std_logic:= '0';
--
begin
PICOBLAZE: kcpsm3
port map(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset_kcpsm3,
clk => clk);
program_rom: rom_0
port map( address => address,
instruction => instruction,
clk => clk);
--
--
reset_kcpsm3 <= RST;
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-- Switches, and LEDs connections and USB/FIFO control register connections
----------------------------------------------------------------------------------
sws_int <= SWS;
LEDS <= leds_int;
usb_rd_ena<= usb_ctrl(0);
USB_RD <= not(usb_ctrl(1));
USB_WR <= usb_ctrl(2);
usb_ctrl(7) <= not(USB_RXF);
usb_ctrl(6) <= not(USB_TXE);
--
----------------------------------------------------------------------------------------------------------
-- KCPSM3 input ports
----------------------------------------------------------------------------------------------------------
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id is
-- read Switches at address 02 hex
when "00000010" => in_port <= sws_int;
-- read USB FIFO data at address 10 hex
when "00010000" => in_port <= USB_D;
-- read USB FIFO control register at address 20 hex
when "00100000" => in_port <= usb_ctrl;
when others => in_port <= "XXXXXXXX";
end case;
end if;
end process input_ports;
--
----------------------------------------------------------------------------------------------------------
-- KCPSM3 output ports
----------------------------------------------------------------------------------------------------------
--
-- adding the output registers to the processor
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
-- Update LEDs at address 08 hex
if port_id="00001000" then
leds_int <= out_port;
end if;
-- Update USB FIFO data register at address 10 hex
if port_id="00010000" then
usb_data <= out_port;
end if;
-- Update USB FIFO control register at address 20 hex
if port_id="00100000" then
usb_ctrl(0) <= out_port(0);
usb_ctrl(1) <= out_port(1);
usb_ctrl(2) <= out_port(2);
end if;
end if;
end if;
end process output_ports;
--
-- FPGA drive USB data bus all the time and only relase it when (usb_rd_ena) signal high
--
USB_D <= (others=>'Z') when (usb_rd_ena='1') else usb_data;
--
end Behavioral;