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Guidelines_English_Final
تحميل الدليل التدريبي

أسئلة شائعة


 

EE616 – VLSI Layout and Processing

Instructor: Prof. Shuja Ahmad Abbasi

Office: Room 2C94, Tel # 467-6729

Text Book:  Silicon VLSI Technology: Fundamentals, Practice, and Modeling, 2008

                  Authors: James D. Plummer, Michael D. Deal, Peter B. Griffin.

Grading Policy: Grades will be distributed as follows;

Two in-term exams (20% each)                                    40%

• Quizes/Class/Home work                                              10%

Term Paper                                                               10%

Final Exam (covers the entire course content)                   40%

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Total Grade                                                                100%

A student will not be given a make-up exam unless he presents an official excuse.

Attendance:

A student with an absence of 25% or greater by the last day of classes will not be allowed to attend the final exam. Tutorials will be included in the absence rate.

Course Content:

Ø  Advanced Silicon Process Technology: Lithography, Oxidation, Diffusion, Ion Implantation, Film Deposition etc.)

Ø  Advanced VLSI Processes – Bipolar, NMOS, CMOS, Bi-CMOS etc.

Ø  Low level and High level VLSI design techniques

Ø  ASIC Design

Ø  Programmable ASIC Design

Ø  CAD Tools for VLSI Design

 
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